This invention relates to frequency synthesizers, particularly to high radio frequency synthesizers. (2) Brief Description of Related Art
In the field of wireless communication where a large number of channels are crowded in narrow high frequency ranges, frequency synthesizers are widely used to generate stable frequencies for transceivers either as the transmitting frequencies or the local oscillator frequencies to beat with the receiving signals. A frequency synthesizer is a phase locked loop (PLL) with a basic circuit shown in FIG. 1. The phase detector 1 generates an output signal which is function of the difference between the phases of two input frequencies. One of the frequencies is a reference frequency Fr derived from a crystal oscillator which generates a fixed stable frequency. The other frequency Fo is a derived from a voltage-controlled oscillator (VCO) 3 and divided by a frequency divider 4. The phase detector 1 output is filtered by a low-pass filter 5 and dc component of the error signal is applied to the VCO. The signal fed back to the phase detector 1 the VCO output frequency is divided by a factor of M. The VCO control voltage Vctrl forces the VCO to change frequency in the direction that reduces the difference between the reference frequency and the divided output frequency Fo. If the two frequencies are sufficiently close, the PLL feedback mechanism forces the two-phase detector input frequencies to be equal, and the VCO is xe2x80x9clockedxe2x80x9d with the incoming frequency.
The frequency of the VCO is usually controlled by a varactor, whose capacitance varies with applied dc voltage. A varactor is a reversed biased junction diode, which resonates with an inductor to cause oscillation. To reduce phase noise, the resonant LC circuit of the oscillator should have low series resistance (i.e. high quality factor Q). The varactor diode contributes substantially to the series resistance, since it is fabricated with semiconductor material. To reduce the series resistance, the varactor diode is preferably fabricated with highly doped, low resistivity semiconductor material. Unfortunately, low resistivity semiconductor material also reduces the tuning range of the varactor diode.
To increase the tuning range of the varactor, Welland proposed in U.S. Pat. No. 6,137,372 to use a coarse tuning arrangement in conjunction with fine tuning for the VCO. A discretely variable capacitance provides the coarse tuning adjustment, and a continuously variable capacitance (i.e. varactor) provides the fine tuning. In such a scheme, the varactor tunes the frequency over a narrower range than the overall tuning range, and allows a high Q resonant circuit to be used. While the fine tuning is obtained with an analog PLL system, the coarse tuning is achieved with quantized signal level feedback loop for digitally controlling VCO frequency in discrete steps. In the coarse tuning step, an arbitrary initial control voltage is applied to the VCO. The output frequency is divided and compared with a reference frequency to generate an error digital signal to reset the digital-control voltage of the VCO by selecting one of a number discrete capacitors in the VCO such that the divided output frequency of the VCO is closer to the reference frequency. After the coarse tuning, the operation is switched to the fine tuning mode using the final coarse frequency as initial frequency for the analog PLL to lock the VCO. The Welland coarse-fine tuning scheme has two major drawbacks: First, the initial control voltage for the VCO, which is randomly selected, is such that xe2x80x9cthe error (digital signal) may be too greatxe2x80x9d to fall outside the lock-in range of the feedback loop, then another initial voltage must be selected by cut-and try. Such a cut-and-try selection of the initial control voltage may slow down the operation. Another drawback of Welland scheme is that the coarse tuning requires dividing the VCO frequency and comparing with a reference frequency in a feedback loop. The frequency division and comparison in a closed feedback loop undesirably increase the settling time and reduces the capture range of a PLL than an open-loop.
An object of this invention is to widen the tuning range of a phase-locked loop for frequency synthesizers. Another object of this invention is to automatically coarse tune the VCO close to the final tuning range for fine tuning. Still another object of the invention is to reduce the settling time of a PLL during coarse tuning of the VCO. Still another object of this invention is to increase the capture range of a PLL during coarse tuning of the VCO. A further object of this invention is to reduce the cycling time during the coarse tuning period.
These objects are achieved by using a coarse tuning in conjunction with a fine tuning of the VCO. The coarse tuning is accomplished without frequency division and comparison in a closed feedback loop. During the coarse tuning, the initial control voltage sets the VCO to generate a frequency in the middle of the frequency range of interest. The initial VCO frequency or divided frequency is compared with a reference frequency. The difference or error frequency is used to digitally control the VCO and to select one of a number of discrete capacitors to coarse-tune the VCO close to the reference frequency. The coarse-tuning is provided by means of binary search without closing the feedback loop. The maximum frequency range is divided into n bit digital values i.e. M=2n, which digitally control a number of discrete frequencies and the coarse tuning tunes the VCO to within one half of the least significant bit of the frequency. The maximum number of steps to tune within one half of the significant bit is (nxe2x88x921) times. After the digitally controlled coarse tuning, the analog phase-locked loop is closed to fine tune the VCO as in a conventional synthesizer.